Eliyan, Fulltime
Staff DFT Engineer, Santa Clara, CA
Job Summary:
Join the leading chiplet startup! As an Eliyan Staff DFT Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining and implementing scan, BIST, 1149, and reporting coverage. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
- Define DFT strategy, methodologies, and implementation plan
- Implement DFT features in RTL for digital and analog blocks
- Run ATPG and create and simulate DFT vectors
- Generate and insert TAP/JTAG interface for chiplet/IP designs
- Work with Analog/Mixed Signal (AMS) teams to ensure DFT coverage for high-speed interfaces
- Work with circuit architects on boundary scan and loopback capabilities
- Prepare vectors for post-silicon bring up (DVT vs. ATE)
- Report status of DFT test coverage and mitigation strategy to narrow down holes
Minimum Qualifications:
- General knowledge of digital and AMS circuit design techniques
- Broad knowledge of DFT methodologies and tools
- Proficient in Verilog/System Verilog and scripting
- Ability to work collaboratively with cross functional team
- Prepare test vectors and collateral for ATE test team
- BS EE or equivalent, with 6-9 years of experience
Ideal Qualifications:
- Breadth of expertise in MBIST, JTAG, IEEE1500, 1149, 1687, 1838
- Provide balanced tradeoffs of test time vs complexity vs coverage
- Ability to create DFT collateral for IP
- 3+ experience with Siemens Tessent MBIST, Scan Insertion and SSN flow
- MS/PhD EE or equivalent, with 6-9 years of experience
