This position could also be based in Austin
We are looking for an experienced DFT Manager to join our dynamic team. In this role, you will lead the Design-for-Test (DFT) strategy across the product development lifecycle, ensuring high-quality, testable, and efficient designs. With 15+ years of relevant experience, you will manage and mentor a team of DFT engineers while driving best-in-class methodologies for robust and reliable semiconductor products.
Key Responsibilities:
- Develop and implement DFT methodologies and strategies to enhance test coverage, minimize costs, and optimize production yield.
- Define and review DFT specifications, including scan, test compression, boundary scan, memory BIST, and ATPG patterns, ensuring compliance with industry standards.
- Select and apply DFT techniques based on design complexity, test coverage needs, and time-to-market constraints.
- Collaborate with design teams to integrate DFT requirements without compromising performance, power, or area.
- Lead and mentor the DFT engineering team, fostering technical growth and professional development.
- Work closely with cross-functional teams (design, verification, manufacturing) to ensure seamless DFT implementation throughout the product lifecycle.
- Drive continuous improvement initiatives to enhance DFT methodologies, tools, and processes.
- Oversee DFT sign-off activities, including ATPG fault coverage analysis, timing analysis, first-pass silicon bring-up, and post-silicon debug.
- Stay updated on emerging DFT techniques and industry advancements, applying best practices to improve internal processes.
Requirements:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of experience in DFT, with expertise in digital and mixed-signal designs within the semiconductor industry.
- Strong proficiency in DFT tools and methodologies, including ATPG, scan insertion, and test pattern generation for complex designs.
- Hands-on experience with EDA tools for scan compression, boundary scan, memory BIST, and JTAG.
- Knowledge of silicon bring-up and post-silicon debug.
- Deep understanding of DFT standards, such as IEEE 1149.1.
- Experience with scripting languages (Perl, Python) for automation and data analysis is a plus.
- Strong analytical and problem-solving skills, with the ability to address DFT-related challenges efficiently.
- Proven leadership and communication skills, with experience managing teams and collaborating across functions.
- Detail-oriented and self-motivated, with a commitment to delivering high-quality results on schedule.
This is an exciting opportunity to play a key role in shaping our DFT strategy and contributing to the development of cutting-edge semiconductor products. If you have the expertise and leadership skills to drive innovation in DFT, we encourage you to apply!
