Technical Staff Engineer - ASIC Design
Responsibilities include:
- Perform RTL design of IP and SoC sub-systems, as well as integration into SoCs, by working with cross-functional teams globally.
- Pre-silicon verification support and debug.
- Emulation and debug of the IP and solution.
- Post-silicon integration, bring-up, and validation.
- Learning and dynamically applying knowledge of the SoC, protocols and standards.
- Effectively presenting technical information to small teams of engineers.
- The role and responsibilities will grow with the individual candidate's skills and interests.
- Ownership of complex digital integrated circuits at the block, subsystem or device level, which are coded in Verilog, System Verilog.
- Translate complex architectural requirements into microarchitecture that is realizable in targeted technology node.
- Lead and mentor fellow design engineers; scope and schedule deliverables.
- Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents.
- Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems.
- Communicate with architects to justify design implementation decisions and associated trade-offs.
- Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds.
- Become versed in applicable storage and computer interface protocol standards.
Requirements/Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent.
- 12+ years related experience.
- RTL Design - Experience in RTL Design using System Verilog.
- Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control.
- Scripting and programming skills using csh, bash, perl, python, tcl, etc.
- Excellent analytical and debugging skills and the ability to proactively solve issues.
- Experience with integration of 3rd party IP.
- Experience with integration of high-speed, mixed signal IP.
- Familiar with low power methodology and flows.
- Working knowledge of DFT.
- Experience with protocols and interfaces is an asset (PCIe, NVME, SAS, DDR, AXI).
- Experience with Formal Verification a plus.
- Excellent analytical, communication (written and verbal), and documentation skills.
- Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment.
Please send an updated copy of your resume to jerald.baker@motektech.com