Job Title: RTL Design Engineer
Duration: Full Time
Location: Mountain View, CA
Job description :
- Handle scripting (memory sweeps) - automation (python)
- Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience required.
- Logic design /micro-architecture / RTL coding is a must.
- Expertise in Verilog & System Verilog is a must.
- Experience in Synthesis / Understanding of timing concepts for ASIC is required.
