Role: Contract Engineering Mid.
Location: Burlingame California 94010
Duration : This is long term contract
Job Description:
Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification IPs integration Understand Design for Verification concepts Drive the top-level µArchitecture definition and develop the necessary RTL Drive the chip-level integration, verification plan development and verification Supervise the RTL-to-GDS flow and assist with synthesis and timing closure Support the test program development, chip validation and chip life until production maturity Work with FPGA engineers to perform early prototyping Support hand-off and integration of blocks into larger SOC environments Assist with Algorithm analysis, verification and improvement Contribute to ASIC digital architecture, design and verification
What We Are Looking For:
Experience as a Digital Design Engineer
Experience in RTL coding, synthesis and/or SoC Integration Experience in digital design µArchitecture BS Electrical Engineering/Computer Science or equivalent experience with UPF based simulation flow System Verilog OVM/UVM experience
Tcl and Python (or similar) scripting experience in SoC integration and ASIC architecture
Wish List/ Nice to Have:
Experience in DFT/Testability requirement and test program definition Experience using High Speed interfaces like PCIe, USB, MIPI FPGA design Tensilica DSP, TIE, CNN, fixed point, floating point, python.
Experience with Power Aware GLS flow
MSEE/CS or equivalent experience
Thanks & Regards,
Ravina Bolgam |US IT Recruiter
#LI-RB1
