We are open contract, contract to hire, or full-time.
Will consider relocation and H1 transfers.
Requirements:
· BS or MS in Electrical or Computer engineering.
· 10+ years of experience in chip development & familiarity with ASIC CAD & EDA tools
· Experience with Synopsys synthesis & STA tools.
· Experience with high gate count ASICs
· Strong Verilog design, Lint, Synthesis, STA & DFT.
· Strong hierarchical synthesis, STA, Lint, CDC & LEC methodologies,
· Solid experience in Hierarchical Synthesis & Static timing analysis.
