One of our client which is having operations globally is looking for Design Verification engineer for an onsite role to Sunnyvale, CA and Austin, TX . Please find the below job description and request you to share me your resume to srinath.k@programmers.io
Title: Design Verification Engineer
Duration: Full time
Location: Onsite to Sunnyvale, CA and Austin, TX
Description:
- Design Verification Engineering Services
- Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests
- Integration/development of C tests/Application Programming Interface (“APIs”) and software build flow
- Integration of UVM testbenches
- Test development and debug, including without limitation tests for functionality, power, performance, error, and connectivity, both for RTL and Gate Level Netlist Design Under Test, tests for functional and code coverage improvements
- Continuous integration and/or regression testing setup and debug for simulation at both RTL and Gate Level Netlist
- Unified Power Format (“UPF”) power aware simulation/emulation
- XProp simulation/regression TestBench creation and maintenance
- Coverage collection and closure
- Documentation of tests, testbench, use-cases, exclusions, and status
