Job Tittle: Engineer IV
Duration: 8 Months (Possible Extension)
Location: San Jose, CA
Job Responsibilities:
- Concept Development: Responsible for the further development of concepts and methods for EDA design environments, focusing on analog/mixed signal ASIC design in advanced nodes.
- PDK Management: Solid understanding of PDKs, effectively managing PDK libraries and collaterals, and driving migration of design environments for incremental releases.
- Calibre Physical Verification: Development of Calibre Physical Verification decks for CMOS PLANAR and FINFET technologies, including DRC, LVS, PERC, FILL, LPE, and shape generation decks and scripts.
- Layout Automation: Layout automation and utilities development using Cadence SKILL/SKILL++.
- Tool and Flow Development: Development and validation of PV tools and flows like parasitic extraction, EMIR drop, and substrate noise analysis.
- Quality and Testing: Responsibilities include testing, validation, customer support, new tool/method evaluations, development of methods and procedures for quality improvement, and automation of deck/techFiles generation and validation.
- Cadence Platform Experience: Experience with the Cadence custom IC Virtuoso platform to create layout test structures, validate verification rules, and troubleshoot errors.
- Physical Verification Tools: Experience with physical verification tools such as DRC, LVS, and parasitic extraction (e.g., Calibre, starRC, ICV) is a plus.
- Revision Control: Working knowledge of revision control software (Git, Perforce, Subversion, Synchronicity, etc.).
- IT Collaboration: Collaborate with the IT team to fulfill advanced node-specific requests (Linux, Exceed-on-Demand, Grid, VMWare-ESX, Storage-system, etc.).
- Global Support: Ensure operation and support within the CAD/IT team for all ASIC designers worldwide.
- Quality Management: Manage the quality and ISO26262 requirements for the EDA tools, both for in-house developments and vendor products.
Skills and Qualifications:
- Personality & Work Ethic: Communicative, problem-solving mindset, responsible, initiative-driven, flexible, and target-oriented. Comfortable working in a fast-paced, dynamic environment with changing priorities.
- Experience & Knowledge:
- Minimum of 8+ years of development experience in Mixed Signal CAD design flows from front to back.
- Expert knowledge and experience with state-of-the-art design tools (EDA vendors such as Cadence, Synopsys, Mentor).
- Proficient in software development methodologies and tools (Linux, scripting and programming languages, and Cadence Skill).
- Thorough understanding of custom analog development flow, design tools, and software/hardware environments.
- Technical Skills: Cadence SKILL, Calibre SVRF/TVF, Python, Shell Scripting.
- Education:
- University degree (Master/PhD) in Electrical Engineering or a comparable subject.
- Ability to identify and analyze tasks efficiently, develop pragmatic application-specific solutions, and communicate effectively.
- Relevant experience in problem-solving methodologies and collaboration/leadership within international and cross-functional teams.
