· Logic design /micro-architecture / RTL coding is a must.
· Expertise in Verilog & System Verilog is a must.
· Experience in Synthesis / Understanding of timing concepts for ASIC is required.
· Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
· Hands on experience in Multi Clock designs, Asynchronous interface is a must.
· Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.
· Knowledge of low power concepts and experience is a plus.
