The Company
Our client is a global leader in technology and has been transforming the electronics we use every day – TVs, smartphones, wearable devices, tablets, etc. since 1969. Since being established, our client has grown into a global brand and is now one of the leading technology companies in the world and a reputable, globally recognized brand.
The Role
The Verification Infrastructure team is looking for a highly motivated Engineer with experience in Design Verification flows and solutions. In this role, you will be responsible for creating and maintaining complex, scalable, and efficient Verification workflows. Key responsibilities include managing regression systems, addressing interactive user requirements, triaging regression failures, overseeing revision control systems, and collaborating with external EDA vendors.
The Individual
As the ideal candidate you will have the following skill and experience:
- Have 5+ years of experience with automation and scripting needed for verification
- Working knowledge of Verilog, UVM, SV and SVA
- Experience with FE CAD tools.
- Previous experience working with multiple EDA vendors that support the integration of EDA Verification Tools.
- Must have knowledge of verification tools (Simulators, Waveform)
- Experience with synthesis, static timing analysis, and ATPG modeling.
- Experience on scripting using Perl, Ruby, Python, tcsh, zsh, and Makefile
- Knowledge of SQL style databases and query commands
- MSEE or BSEE with 5+ years relevant experience preferred (or equivalent education and experience)
APPLY NOW – INTERVIEWING IMMEDIATELY
Location: San Jose, CA (The role is hybrid and will be onsite 3x per week)
Salary: $80-110/hour on a W2 basis
Contact Details: Ashton.murray@consolpartners.com