""MINIMUM 08 YEARS OF EXPERIENCE REQUIRED""
Job Responsibilities:
- Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors
- Drive frontend and backend implementation from RTL to gds2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementation
- Would be responsible for hands-on physical implementation and timing closure of core platforms and SoC's
- Working with the Systems and Application team to drive timing closure-friendly SoC architecture and IO interfaces/IO pin
- Streamlining the timing signoff criterions, timing analysis methodologies and flows (critical path spice simulation ) and develop/enhance auto ECO generation scripts for timing closure
- Responsible for floor planning, physical synthesis and physical design closure of large complex designs.
If you are interested, please share your resume at SACHIN.VERMA@QUEST-GLOBAL.COM