About HCLTech:
HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Engineering Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. To learn how we can supercharge progress for you, visit https://www.hcltech.com/about-us.
Job Description:
Location: Bay Area, CA OR Austin, TX
Need person with Emulation model build, transactor integration and debug experience (Palladium) –
- ASIC/IP RTL to Emulation platforms (Preferred: Palladium)
- Build model from released RTL
- Generate target platform loadable image(s) test and release the image to Firmware and DV teams
- Run sanity tests for qualifying release of the image(s)
- Release the model to various team including Functional Validation team, Firmware, DV
- Assist debug of failures providing instrumented model ( Waveform Dumps, in circuit debug) and interfacing with stakeholder
- Coordinate with Tools team to validate tool and Model release
- FPGA and Emulator flows and methodologies
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
