Senior RTL Designer Engineer.
Full-time opportunity in Campbell, CA
Responsibilities
· Develop and execute: micro-architecture specification, RTL in Verilog/System Verilog, performance, speed, power goals, and verification
· Bringing up the chip in lab and developing bring-up scripts
· Participate in chip architecture definition, review, verification, and testing
Requirements
· BS/MS in Electrical Engineering or Computer Engineering with 5+ years of relevant experience from design to successful tapeouts and shipping
· 5+ years of RTL design experience and familiarity with writing elegant synthesizable RTL.
· Experience integrating embedded CPU’s into an ASIC design.
· Experience integrating 3rd party Risc V IP core into a design a plus.
· Experience in ASIC DFT and physical design flows and methodologies in 7nm – 16nm process nodes
· Must be familiar with ASIC design tools and/or FPGA design tools
· Experience with Xilinx Vivado a Plus
· Experience programming in Python and/or C++ a plus
· Strong analytical and problem-solving skills.
· Self-motivated and able to work effectively independently and in a team