ASIC/RTL Designer – San Jose
Position Overview
This role focuses on RTL design for ASIC development, where you will be involved in designing, testing, and synthesizing ASICs to meet project requirements. You will work with industry-standard tools and participate in various stages of the design process, from concept through tape-out. The position requires a solid technical background in RTL coding and ASIC design methodologies.
Key Responsibilities
- RTL Design: Utilize Verilog-HDL and System Verilog to design, implement, and simulate RTL code.
- Front-End Tools: Work with tools such as NCVerilog, NCSIM, and Simvision for simulation, and perform linting and other verification tasks.
- Design for Test (DFT): Ensure RTL code is DFT friendly, understanding the scan concept and integrating DFT methodologies into design.
- Synthesis and Timing: Conduct synthesis, CDC analysis, and static timing analysis to ensure the design meets timing constraints and functional requirements.
- Post-Layout Simulations: Perform SDF-annotated simulations, with a solid grasp of parasitic delays to assess timing and functionality after physical implementation.
- Tape-Out Process: Understand the tape-out process and supply chain for integrated circuit product development, ensuring seamless transition from design to fabrication.
Required Qualifications
- Master’s degree in Electrical Engineering or Computer Engineering (MSEE/CE) or equivalent.
- At least 8 years of experience in RTL design.
- Proficiency in Verilog-HDL/System Verilog coding.
- Strong experience with simulation and verification tools such as NCVerilog, NCSIM, and Simvision.
- Knowledge of DFT principles and the ability to write DFT-friendly RTL code.
- Expertise in synthesis, clock domain crossing (CDC) analysis, and static timing analysis.
- Experience with SDF-annotated simulations and understanding of parasitic delays.
- Familiarity with the tape-out process and semiconductor supply chain.
Preferred Qualifications
- Knowledge of microarchitecture, including standard peripherals such as AMBA BUS, I2C, SPI, and UART.
- Experience with high-speed DSP applications and algorithms.
- Deep understanding of signal integrity and power integrity in high-speed designs.
- Familiarity with Verilog AMS simulation.
- Experience creating behavioral models of analog circuits.
- Willingness to take on a multi-functional role and collaborate with cross-disciplinary teams.
- Strong written and verbal communication skills, with the ability to present to technical and management teams.
- Proactive and creative problem-solving approach with a focus on innovation and collaboration.
- Excellent time management, organizational, and interpersonal skills.
