Job description:
Need person with Emulation model build, transactor integration and debug experience (Palladium)
- ASIC/IP RTL to Emulation platforms (Preferred: Palladium)
- Build model from released RTL
- Generate target platform loadable image(s) test and release the image to Firmware and DV teams
- Run sanity tests for qualifying release of the image(s)
- Release the model to various team including Functional Validation team, Firmware, DV
- Assist debug of failures providing instrumented model ( Waveform Dumps, in circuit debug) and interfacing with stakeholder
- Coordinate with Tools team to validate tool and Model release
- FPGA and Emulator flows and methodologies
- Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
