Lead Digital SerDes Architect - Colorado, U.S.
Responsibilities:
- Lead the architecture design, RTL development, constraint generation, synthesis, timing analysis, and verification for SerDes designs, ensuring documentation and support throughout the process
- Drive the RTL design process, verification, synthesis, lint and CDC analysis (e.g., Spyglass), constraint development, and timing model generation using PrimeTime
- Lead coordination efforts across geographically dispersed teams and independently determine procedures for new assignments
- Serve as the primary point of contact for customer queries, managing databases, and necessary tools
Requirements:
- Requires BSEE and at least 15+ years of experience with SerDes architecture with an emphasis on digital/mixed-signal interfacing
- Comprehensive knowledge of SerDes architecture, protocols, and integration
- Experience with high-level RTL design to synthesis
- Experience using spyglass, VC spyglass, design compiler, and Primetime
- Knowledge of VLSI design tools for lint, CDC, synthesis, verification, DFT insertion, timing analysis
