Position: CPU RTL Design Engineer,
Location: San Jose, CA (Onsite/Remote)
Job Description:
- Design and develop IP’s, Subsystems, SOC integration.
- Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Microarchitecture development and specification - From early high-level architectural exploration, through micro architectural research and arriving at detailed specification.
- Excellent track record in designing IP’s, Subsystems involving CPUs, bus interconnects.
- Working experience on Fetch Unit, MMU/IO-MMU, Load-Store, RISCV-Privilege Architecture, Advance Interrupt Architecture.
- Worked with IP’s or Subsystem involving CPUs like RISC-V, ARM or x86 is a big plus.
- Knowledge of AMBA bus protocols, DMA concepts.
- Hands on experience with RTL coding using SV, Verilog, scripting language (Perl, Python, shell, TCL).
- Experienced with EDA tools, RTL coding, low power techniques, Lint, CDC and timing.
- Knowledge of logic design principles along with timing, performance and power implications.
