Provide design verification services for our PCIe/CXL Switch SoCs
Responsibilities
- Test bench development using System Verilog and UVM
- Test plan and test case development
- Experience in developing SV Functional coverage models and SVA assertions and cover properties
- Regression setup and debug RTL level and gate level simulations working with design team
Requirements
- 5 to 10 years of Design Verification experience with multiple successful tape outs
- Deep knowledge about System Verilog, UVM and verification coverage matrix
- Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)
- Familiar with Synopsys PCIe/CXL Verification IPs
- Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
- Proficient in Perl/Python scripting
