Desired Skills and Experience
- BSEE and 8 years’ experience required, or MSEE and 6 years, or PhD and 3 years. MSEE preferred
- Demonstrated Analog IC design experience using SOI CMOS
- Proficient with Cadence tools and solid understanding of general analog circuits such as bias, bandgap, LDO, opamp, charge pump, temperature sensor
- Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on IC
- Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance
- Demonstrated experience debugging, resolving and applying techniques to mitigate analog signal noise coupling and optimum layout for performance, and die size trade off
- Layout experience using Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on analog layouts
- Good understanding of MIPI standard
- Good communication and presentation skills
Job Description
-Circuit architecture, planning, design, simulation, verification, and production ramp support of highly integrated, high-volume ICs for high-growth, fast-paced, and competitive wireless handset market
- Knowledge of RF area circuit experience a plus
-Familiarity with cellular standards will be useful
- Good understanding of semiconductor physics and strong circuit intuition/simulation skills utilizing Cadence is necessary
