Responsibilities:
- Define verification strategy, requirements, test environments for IP level verification.
- Create test plans and write tests to provide complete features coverage.
- Own verification for complex IPs, including creating test plans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
- Develop and implement technical solutions to complex quality and design challenges.
- Write scoreboards, sequences, constraints, assertions and functional coverage.
- Write make files and scripts for verification infrastructure.
- Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
- Lead small teams of verification engineers and mentor engineers.
- Collaborate with teams across sites and geographies.
Qualifications:
- Required/Minimum Qualifications
- 10+ years of technical engineering experience
- OR bachelor's degree in electrical engineering, Computer Engineering, or related field AND 5+ years of technical engineering experience
- OR master's degree in electrical engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field
- 7+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals
- In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments
- Solid understanding of computer architecture
- Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
- Scripting language such as Python or Perl or shell scripts
- Prior experience with high performance DMA verification
- Additional or Preferred Qualifications
- 10+ years of technical engineering experience
- OR bachelor's degree in electrical engineering, Computer Engineering, or related field AND 8+ years of technical engineering experience
- OR master's degree in electrical engineering, Computer Engineering, or related field AND 6+ years of technical engineering experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
- 10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
- Experienced in test plan development to define test cases, checkers, assertions, and functional coverage points
- Experience in verification of many designs at unit level
- Knowledge of verification principles, testbenches, UVM, and coverage
- Knowledge of system verilog class, constraints, coverage and assertions
- Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams
- Proficient in reading, debugging, and/or designing using Verilog languages
Required Skills:
- Minimum 7+ years' experience with ASIC Design Verification (looking for someone who can make sure everything is correct and on schedule utilizing this skillset)
- Minimum 7+ Years's experience with unit level verification
- Minimum 7+ Years's experience of experience in UVM library (UVM is at universal verification)
Preferred Skills:
- A lot of block level verification work experience (goes with unit level verification experience listed in hard skills below)
- Someone who works well with others and has a team-work mindset
Pay range and compensation package: [Pay range or salary or compensation]
Equal Opportunity Statement: [Include a statement on commitment to diversity and inclusivity.]
