OVERVIEW
Our client, a global leader in the semiconductor industry, ranks among the top 5 worldwide. They are renowned for driving innovation in system-on-chip (SoC) technologies, powering over 2 billion devices annually across mobile, home entertainment, connectivity, and IoT sectors. Their technology touches nearly 20 percent of households and supports one-third of the world’s mobile phones.
By collaborating with leading brands, they push the limits of what’s possible—making cutting-edge technology accessible and fostering innovation on a global scale.
KEY RESPONSIBILITIES
- Collaborate with system architects to develop scalable and efficient memory system architectures.
- Lead the design and optimization of memory systems to enhance performance, efficiency, and integration.
- Demonstrate expertise in system-level performance trade-offs, memory subsystems, and technologies (e.g., DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5).
- Design memory systems for automotive applications, ensuring compliance with industry standards like ISO 26262 and Automotive SPICE. (Nice to have)
- Work with the DV team to rigorously verify and test RTL designs.
- Support the software team in troubleshooting memory-related issues.
REQUIRED EXPERIENCE
- Deep understanding of computer architecture, microarchitecture, and performance optimization.
- 10+ years in design, specializing in architecture, RTL design, performance tuning, and power optimization.
- Proven expertise in system-level cache design for automotive applications.
- Familiarity with DRAM standards (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5) and memory technologies.
- Knowledge of ARM processor architectures and microarchitectures is advantageous.
- Experience with AMBA AXI, CHI, and LPDDR4/5 protocols is a plus.
- Strong communication, problem-solving, and debugging skills.
INTERESTED?
We’re eager to present top candidates for this role. For more details, please contact Maria Mercado at PER Recruitment or send your CV to maria.m@per-international.com.
