OVERVIEW
Our esteemed client is a key player in the Semiconductor industry, ranked within the top 5 globally. Renowned for their groundbreaking work in advancing systems-on-chip (SoC) technology, they cater to various sectors including mobile devices, home entertainment, connectivity, and IoT products. Their technology powers over 2 billion devices annually, reaching around 20 percent of households and impacting nearly one-third of the world's mobile phones.
Committed to empowering individuals and fostering innovation, they collaborate with leading international brands to make their cutting-edge technology accessible to diverse audiences, thereby pushing the boundaries of possibility
KEY RESPONSIBILITIES AND ACTIVITIES INCLUDE
- Partner with system architects to develop a robust and scalable memory system architecture.
- Lead the creation and refinement of memory system designs to enhance efficiency, performance, and implementation.
- Possess a deep understanding of system-level performance trade-offs, system architecture, memory subsystems, and various memory technologies (e.g., DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5).
- Design and customize memory systems for automotive applications, ensuring validation, enhancements, and adherence to performance and system requirements.
- Ensure compliance with automotive industry standards and regulations such as ISO 26262 and Automotive SPICE.
- Collaborate with the DV team to rigorously test and verify RTL designs.
- Assist the software team in resolving issues related to memory systems.
EDUCATION AND EXPERIENCE REQUIREMENTS
- Strong grasp of computer architecture, microarchitecture, and performance dynamics.
- Extensive knowledge of automotive standards and regulations (e.g., ISO26262).
- Over 10 years of experience in design, including expertise in architecture, RTL design, performance analysis, and power optimization.
- Proven track record in designing and optimizing system-level cache for automotive applications.
- Proficient in automotive-grade DRAM interface standards and memory technologies, such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, and LPDDR5.
- Experience with system cache, memory controllers, or DDRPHY related to safety and security.
- Familiarity with modern ARM processor architectures and microarchitectures is advantageous.
- Understanding of AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus.
- Excellent communication, problem-solving, root cause analysis, and debugging skills.
INTERESTED?
We are keen to submit suitable candidates for this role to our client promptly. For more information, reach out to Maria Mercado at PER Recruitment or email your CV to maria.m@per-international.com.
