OVERVIEW
Our esteemed client is a key player in the Semiconductor industry, ranked within the top 5 globally. Renowned for their groundbreaking work in advancing systems-on-chip (SoC) technology, they cater to various sectors including mobile devices, home entertainment, connectivity, and IoT products. Their technology powers over 2 billion devices annually, reaching around 20 percent of households and impacting nearly one-third of the world's mobile phones.
Committed to empowering individuals and fostering innovation, they collaborate with leading international brands to make their cutting-edge technology accessible to diverse audiences, thereby pushing the boundaries of possibility
Key Responsibilities
- Collaborate with system architects to develop competitive and scalable interconnect architecture.
- Lead the design and optimization of NoC Interconnect and Memory Systems to enhance power, performance, and implementation.
- Demonstrate a comprehensive understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (e.g., DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5).
- Develop and implement NoC Interconnect for automotive applications, validating functionality, refining design revisions, and meeting performance targets and system requirements.
- Ensure all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.
- Collaborate with the DV team to thoroughly verify RTL design.
- Assist the software team in resolving issues related to NoC interconnect and Memory Systems.
Desired Skills and Experience
- Strong knowledge of computer architecture, microarchitecture, and performance optimization.
- In-depth understanding of automotive requirements and standards (e.g., ISO 26262).
- Over 10 years of relevant design experience in architecture, RTL design, performance analysis, and power optimization.
- Proven experience in designing and optimizing interconnects for automotive applications.
- Experience in developing fail-operational interconnect architectures for functional safety.
- Familiarity with recent ARM processor architectures and microarchitectures is advantageous.
- Knowledge of AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is beneficial.
- Excellent communication, problem-solving, root-cause analysis, and debugging skills.
INTERESTED?
We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Maria Mercado at PER Recruitment or send your CV at maria.m@per-international.com
