Fantastic GROUND-FLOOR opportunity...
This very promising well-funded startup is looking for passionate Founding Engineer’s who have significant experience with VLSI front-end design flows and strong EDA coding skills to build the co-pilot for chip designers. It is a terrific opportunity to start from the ground-up and make a real and significant contribution, as they unleash this existing, yet totally new approach to CHIP DESIGN.
Chip teams today are still using the same archaic workflows from 30 years ago, resulting in lengthy 12-18 month design cycles and the inability to ship chips fast enough to keep up with the software pointer…
THIS COMPANY IS CHANGING THAT!!!!
· Their chip design co-pilot is helping chip designers autonomously design correct and optimize chips, which allows chip/IP companies to build better chips in less time.
· This startup is well-funded by top investors and is already generating revenue with customers that are world-class chip and IP design companies. The interest and demand for their deliverables has outpaced their ability to build and ship the product, making the need for talented engineers even more critical.
· They want engineers that are excited about transforming the way chips are built; engineers that can leverage their understanding of functional correctness and PPA optimization in RTL design to develop key co-pilot features that make building chips much faster, easier, and more intuitive.
· You’ll work directly with their world-class customers building advanced chips and IP and iterate on the product, getting direct customer feedback.
· You will help deliver product updates on a weekly basis, collaborate in-person in the Bay Area, and geek out about semiconductor news (they sponsor SemiAnalysis subscriptions for team members!).
What you’ll do:
· Write code (Python/C++) and make software architectural decisions for key product features...THIS IS A SENIOR CODING POSITION!
· Translate user feedback to product updates/features
· Be part of planning core product roadmap and strategy with the founders
Minimum requirements:
· Passionate and excited about chips and AI for EDA
· Have experience designing ASICs using SystemVerilog and synthesis/verification tools (open-source and/or commercial)
· Good at shipping high-quality code (Python/C++) quickly
· Basic knowledge of statistics & AI/ML methods
· Resilient, data-driven, and works from first principles
Ideal requirements:
· Proven tapeouts (ideally on advanced technology nodes)
· Contributor to open-source EDA/chip efforts
· Significant experience with PPA optimization and/or functional correctness convergence
