Power Analysis : 8 to 14 Years Experience
Work Location : Bay Area or Austin or Remote from anywhere
Responsibilities
- Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design at different design stages from RTL to gate-level netlist.
- Contribute to develop, improve, and automate power analysis flows
- Investigate power inefficiencies and provide feedback to design teams
- Present the results in a weekly meeting to wider audience
- Work closely with physical design team for clock tree, floorplan and physical implementation optimization.
- Participate in memory power optimization through memory selection and traffic optimization.
- Perform Synthesis and Physical design trials for optimal PPA recipes.
Minimum Qualifications
- RTL2GDSII design flow usage & development in advanced technology nodes (7nm and below)
- Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF usage.
- Experience in power analysis and reduction using PrimeTime PX/PrimePower
- Proficiency in scripting languages such as Python and/or Perl is required
- Proficiency with TCL is required
- Familiarity with low power implementation techniques, clock gating, power gating etc.
- Familiarity with memories (SRAM/DRAM/RF/Flop based fifos)
Preferred Qualifications
- Experience with synth, PnR flows
- Power and performance implications with latest technology nodes
- Proficiency with version control systems
- Experience with rtl power optimization using tools such as Power-Artist
- Experience with library characterization tools and analysis
- Experience with FSDB analysis for design profilin
