Acceler8 Talent has teamed up with a cutting-edge company that’s transforming AI hardware, with a focus on maximizing performance for large language models (LLMs) like GPT.

Their tech is all about balancing performance and cost efficiency, offering competitive latency and deep hardware control. With scalable hardware, they’re speeding up model development and making it more accessible for researchers and startups.

Founded by two former FAANG leaders, this company is driving the future of AGI, delivering end-to-end solutions from silicon to systems.

They’re now on the hunt for a skilled Microarchitect ready to make a big impact in the world of AI.

Responsibilities:

Contribute to scalable silicon architecture-to-design methodology across blocks, subsystems, and full-chip design.
Own subsystem or chip-level design deliverables from micro-architecture to sign-off.
Plan and lead reviews on micro-architecture, design specs, and timing closure towards key silicon milestones, including tapeout.
Collaborate with verification, DFT, and physical design teams to achieve top performance-power-area results.

Requirements:

End-to-end experience in silicon design for ASICs and SoCs, from architecture to production.
Proficiency in SystemVerilog, Python, C/C++, Bluespec, and similar languages.
Proven experience in micro-architecture and design for high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, and memory management.
Experience in design testing, verification, synthesis, and design sign-off processes.
Familiarity with DFT and physical design methodologies to achieve optimal test coverage, timing, power, and area.
Silicon debug and bring-up experience is a plus.

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