Location: US - CA - Sunnyvale
Experience Level: 8 + years (Relevant)
This is a similar role to Design verification with experience in Verilog, C/C++, Verification, UVM, System Verilog
Job Responsibilities
- Work with researchers and architects defining verification plans for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Key Projects/Day-to-Day Responsibilities
- Work with researchers and architects defining verification plans for each of the different core IP.
- Define and track detailed test plans for the different modules and top levels.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Education/Experience: Bachelor's degree
