Job Title: Design Verification
Location: US Bay area
No. of Openings: 5; at least 6 years of experience
Job Description:
- Verify functionality.
- Architect and implement simulation test bench in UVM.
- Develop and execute test-plans for verifying correctness and performance of the design.
- Own and debug failures in simulation at multiple levels ( block, cluster and full chip ) to root-cause problems
- Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
