Immediate need for a talented Contract Engineering Associate Mid. This is a 12+ Months Contract opportunity with long-term potential and is located in Burlingame, CA(Onsite). Please review the job description below and contact me ASAP if you are interested.
Job ID:24-37175
Pay Range: $65 - $70/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Note-This role is very similar to RTL design Engineer with strong experience in RTL coding, synthesis, and/or SoC Integration.
Key Responsibilities:
- Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification.
- IPs integration.
- Understand Design for Verification concepts.
- Drive the top-level µArchitecture definition and develop the necessary RTL.
- Drive the chip-level integration, verification plan development and verification.
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
- Support the test program development, chip validation and chip life until production maturity.
- Work with FPGA engineers to perform early prototyping.
- Support hand-off and integration of blocks into larger SOC environments.
- Assist with Algorithm analysis, verification, and improvement.
- Contribute to ASIC digital architecture, design, and verification.
Key Requirements and Technology Experience:
- Experience in RTL coding, synthesis, and/or SoC Integration.
- Experience in digital design µArchitecture.
- Familiarity with Verilog, System Verilog coding.
- 5+ years of experience as a Digital Design Engineer.
- Experience in RTL coding, synthesis, and/or SoC Integration.
- Experience in digital design µArchitecture.
- BS Electrical Engineering/Computer Science or equivalent experience.
- Experience with UPF based simulation flow.
- System Verilog OVM/UVM experience.
- TCL and Python (or similar) scripting experience.
- Experience in SoC integration and ASIC architecture.
- Experience in DFT/Testability requirement and test program definition.
- Experience using High Speed interfaces like PCIe, USB, MIPI.
- FPGA design.
- Tensilica DSP, TIE, CNN, fixed point, floating point, python.
- Experience with Power Aware GLS flow.
- MSEE/CS or equivalent experience.
Our client is a leading Electronics Industry, and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.
