DAC Search Inc/Richard Goldstein specializes in Recruiting Services for Semiconductor, EDA, and Artificial Intelligence (AI) Chip companies, primarily startups
Feel free to review my webpage (www.richtherecruiter.com)
My client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they're looking for passionate individuals to join a seasoned and dynamic team. They were the same founding team for a prior startup that was successfully acquired by a "Big Chip" company and they have alot of credibility in the industry. The Board and executive team are very very solid
We are hiring an experienced RTL Microarchitect with a passion for startups and the dynamic environment that comes with the territory and mindset.
The positions are on-site in either Santa Clara, CA or Bengaluru, India. Sorry there are no exceptions. The team is small and the cohesiveness of being together daily is paramount.
The experience we are looking for are "must haves", and can be a combination of skills listed below, namely CACHE COHERENCY, NOC, FABRIC, PIPELINING, INTERCONNECT
- Design and develop microarchitectures for a set of highly configurable IPs
- Microarchitecture and RTL coding ensuring optimal performance, power, area
- Collaborate with software teams to define configuration requirements, verification collaterals etc.
- Work with verification teams on assertions, test plans, debug, coverage etc.
Qualifications and Preferred Skills
- BS, MS in Electrical Engineering, Computer Engineering or Computer Science
- 8+ years and current hands-on experience in microarchitecture and RTL development
- Proficiency in Verilog, System Verilog
- Familiarity with industry-standard EDA tools and methodologies
- Experience with large high-speed, pipelined, stateful designs, and low power designs
- In-depth understanding of on-chip interconnects and NoCs
- Experience with in ARM ACE/CHI or similar coherency protocols
- Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoCs
- Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
- Experience with modern programming languages like Python is a plus
- Excellent problem-solving skills and attention to detail
- Strong communication and collaboration skills
Please apply or email me directly to RICH@DACSEARCH.COM