Job Title: Design Verification Engineer
Job Location: San Jose, CA(Onsite)
Type: Contract
Duration: 12+ Months
Job Description:
- Triage regression failures and make testbench updates.
- Debug functional errors in RTL model using simulation and debug tools.
- Maintain efficient and clean regression status.
- Develop Scalable System Verilog/UVM testbenches for unit level and/or Cluster level verification.
- Review Architecture and Micro-Architecture specifications.
- Closely work with Architects and RTL designers.
- Define, maintain and execute unit level and/or Cluster level verification test plans.
- Generate and run Testcases on logic simulation models.
- Code Functional coverage models and System Verilog assertions.
- Drive Functional Coverage and Code coverage to closure.
Requirements
- Integrate C++ reference model into Scoreboards.
- 5-15 year’s industry experience in a design verification role.
- Proficient in System Verilog/UVM/OVM, OOP/C++
- Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
- Experience with code coverage and functional coverage driven verification methodology.
- Experience in creating, running and debugging of System Verilog/UVM constraint random Testbench.
- Excellent working knowledge of scripting languages such as Python or Perl.
- Understanding of micro-architecture, logic design, FSMs, arithmetic Datapath pipelines.
- Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
- Strong debugging skills
- Strong programming skills with good understanding of algorithms and data structures
- Good verbal and written communication skills.
