8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs.
Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware or similar floating point ALUs), embedded SRAM controllers, ARM/MIPS/RISC-V Architecture (Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation, etc.) and/or familiarity with AMBA/APB/AXI amd processor processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C etc.
Experience integrating 3rd party PCIE controller + Serdes, HBM controller +PHY.
Experience with timing closure at high frequencies, along with familiarity with low power UPF flow, for defining power intent of chips with multiple power domains.
BS/MS in Electrical/Computer Engineering or similar field
