Verilog, Tessent, Genus
Responsibilities:
- Develop and optimize DFT features for use in complex digital systems
- Perform structural scan and at-speed scan insertion, automatic pattern generation, and scan
- coverage analysis (Cadence Genus w/ Modus or Siemens Tessent)
- Create DFT patterns for ATE to enable high volume manufacturing
- Design and contribute to design for test (DFT) methodologies
- Work with designers to integrate DFT flow into a digital tool flow
Basic Qualifications:
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields
Experience:
- Lead is expected to have 5+ years of work experience in DFT
- History of assuming responsibility for a variety of technical tasks and completing projects independently
- Proficient in Verilog for both RTL design and verification
- Proficient in structural scan and at-speed scan design, pattern generation/verification and BIST methods
- Proficient in ASIC DFT insertion (Cadence Genus, Cadence Modus, Siemens Tessent), and verification (NCSIM, VCS, ModelSim) tools
- Proficient in writing timing constraints and deep understanding of timing analysis
- Proficient in scripting or programming languages
- Experience working with version control software, such as Git
Preferred Qualifications:
- Working knowledge of architecting DFT features for ASIC and custom blocks in a digital-top flow
- Experience designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Experience working on digital designs with multiple clock domains and clock dividers
- Performed silicon bring-up, debug, and evaluation
- Programming experience in Python
Knowledge of high-speed SerDes or SerDes components
