**Locations are San Jose, CA; Richardson, TX; and Chandler, AZ**
Responsibilities:
- Layout of Power and Analog integrated circuits for the general power electronics market (mobile, industrial, consumer)
- Floor planning and concept realization of highly integrated analog/power circuits
- Top Level and block level layout designs including circuit and layout verification checks (LVS, DRC)
- Full Analogue layout design and layout size optimization of CMOS JI and SOI
- Interface and cooperation with Analog and Power IC design engineers in asia and US
- Responsibility for tape out process, data documentation and data archiving
- Independent interface with design engineering, foundry and manufacturing
Qualifications:
- 10+ years of relevant work experience, 15+ preferred
- Background in analog power IC fundamentals and experience with integrated analog mixed-signal circuit layouts
- Understanding of semiconductor process technologies like CMOS, BICMOS JI, and SOI
- Proven designs in DC-DC converters, including bucks, boosts, and charge pumps
- Experience working with voltages in 10-60V range.
- Experience leading layout design teams
- Experience with CAD layout tools like Cadence
- Fluent in Vietnamese. (Only for San Jose location)
- Outstanding Analytical and problem-solving skills
